Back in September of last year, I wrote about the transactional memory hardware being used by IBM in the new Sequoia super-computer it is building for the Lawrence Livermore National Laboratory. The technology is expected to make software development for parallel processing easier. Now, according to an article at Ars Technica, Intel plans to bring transactional memory support to mainstream products, beginning with its Haswell chips, due to ship sometime next year. In a blog post announcing the feature, which it calls TSX (Transaction Synchronization Extensions), Intel’s James Reinders explains the basic idea of TSX:
In a nutshell, Intel TSX provides a set of instruction set extensions that allow programmers to specify regions of code for transactional synchronization. Programmers can use these extensions to achieve the performance of fine-grain locking while actually programming using coarse-grain locks.
The post also gives an overview of how the new capabilities can be used. TSX has two application interfaces. The first, called Hardware Lock Elision [HLE] is intended to make easier the porting of existing code, which may use locks. It also makes it possible to have code that will work correctly on both older processors (which don’t support transactional memory) and Haswell. The second, Restricted Transactional Memory [RTM], is intended primarily for new development, and provides more flexible structuring of transactions than is possible with HLE.
Although the idea of atomic transactions should be familiar to anyone who has developed relational data base applications, transactional memory is still pretty new. The TSX capabilities that Intel will provide are very low-level (close to the hardware) functions. Development of higher-level development tools that can take advantage of facilities like TSX is still in the early stages, but the work has started. I think the development holds a lot of promise for easier development of software that can use highly parallel hardware effectively.
Update Monday, 20 February, 10:51 EST
Corrected the chip name to ‘Haswell’, rather than ‘Haskell’. Thanks to Jim Cownie for the correction.